Professor Khaled Hayatleh

This research aims to offer a power supply system based on power converters to supply electromagnetic contactors from the power distribution grid. Its primary purpose is to minimise the voltage sag impact on the contactor, eliminating the possibility of contacts tripping or excessive vibration. In addition to this, the contactor's inherent low power factor must be compensated, reducing the contactor's impact on the power grid. To complete these requirements, the power supply system comprises a Totem-pole PFC converter, a Buck converter stabilising the supplied voltage, and an H-Bridge, decreasing the switch-off commutation time. The research focuses on the converters' design methodology, supported by a case study and experimental verification. Considering the electromagnetic contactor characteristics, the system design requirements are systemised. The analytically and experimentally obtained data shows that based on the chosen converters' topologies, the suggested power supply system provides contactor stable operation in a wide input voltage range, acceptable power losses and high efficiency.

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using Bandgap Reference (BGR). There are mainly 2 types: Current mode and Voltage mode. The current mode bandgap reference (CBGR) is widely accepted in the industry due to the output voltage that is below 1V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, large silicon area, multiple operating points, and large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the Complimentary to Absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (-40 to 125°C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (+/- 3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a Fast process, Hot (125°C) corner. It occupies a silicon area of 81 x 42 µm (including capacitors). This design can aim for biomedical and sensor applications.

Keywords: Bandgap reference; Noise; Operating points; Self-bias; Offset phase-margin

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180nm CMOS process and operating with ±1.8V supply rails, the input resistance is 1.05ohms and the power dissipation is 93.6µW. The bandwidth, for a gain of 100dBohm, exceeded 9MHz. For a 1µA, 1MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09pA/√Hz and with a photodiode capacitance of 2pF is 8.52pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5pF to 2pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

The object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors’ parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace.

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV.

A transformer-less Buck-Boost DC-DC converter in usage for the fast-charge of electric vehicles, based on powerful high-voltage IGBT (Isolated Gate Bipolar Transistor) modules is analyzed, designed and experimentally verified. The main advantages of this topology are: simple structure on the converter’s power stage; a wide range of the output voltage, capable to support nowadays vehicles on-board battery packs; efficiency and power density accepted to be high enough for such class of hard-switched converters. A precise estimation of the loss, dissipated in the converter’s basic modes of operation – Buck, Boost, and Buck-Boost is presented. The analysis shows an approach of loss minimization, based on switching frequency reduction during the Buck-Boost operation mode. Such a technique guarantees stable thermal characteristics during the entire operation, i.e. battery charge cycle. As the Buck-Boost mode takes place when Buck and Boost modes cannot support the output voltage, operating as a combination of them, it can be considered as critically dependent on the characteristics of the semiconductors. With this, the necessary duty cycle and voltage range, determined with respect to the input-output voltages and power losses, require additional study to be conducted. Additionally, the tolerance of the applied switching frequencies for the most versatile silicon-based powerful IGBT modules is analyzed and experimentally verified. Finally, several important characteristics, such as transients during switch-on and switch-off, IGBTs voltage tails, critical duty cycles, etc., are depicted experimentally with oscillograms, obtained by an experimental model. 

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage, and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gainboosting technique. The proposed opamp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing
gain below a 1.1V supply. The circuit draws a total static current of 295μA and occupies 5000μm2 of silicon area.

This paper presents a 65nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5-100mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loopgain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25-50dB gain, and post-layout simulations showed a 15dB reduction in the harmonic distortion for 20mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108μm2 silicon area and consumes 0.43μA from a 1.2V power supply.

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply. 

In this paper we propose a new architecture for enhancing the performance of a transimpedance amplifier (TIA) used for low-currents, and in particular, that used in biosensing. It is usually the first block in biomedical acquisition systems for converting a current in the nanoampere and picoampere range into a proportional voltage, with an amplitude suitable for further processing. There exist two main amplifier topologies for achieving this, current-mode and shunt-feedback mode. This paper introduces a shunt-feedback amplifier that embodies current-mode operation and thereby offers the advantages of both existing schemes. A conventional shunt-feedback amplifier has a number of stages and requires compensation components to achieve stability of the feedback loop. The exemplary circuit described is inherently stable because a high gain is effectively achieved in one stage that has a dominant pole controlling the frequency response. Exhibiting complementary symmetry, the configuration has an input port that is very close to earth potential. This enables the configuration to handle bidirectional input signals such are as met with in electrochemical ampero-metric biosensors. For the 0.35µm process adopted and ±3.3V rail supplies, the power dissipation is 330µW. With a transimpedance gain of 120dBohm the incremental input and output resistances are less than 2ohm and the -3dB bandwidth for non-optical input currents is 8.2MHz. The input referred noise current is 3.5pA/√Hz.

Autonomous vehicles have been shown to increase safety for drivers, passengers and pedestrians and can also be used to maximize traffic flow, thereby reducing emissions and congestion. At the same time, governments around the world are promoting the usage of Battery Electric Vehicles (BEVs) to reduce and control the emissions of CO2. This has made the development of autonomous vehicles and electric vehicles a very active research area and has prompted a significant amount of government funding. This paper presents the detailed design of a low-cost platform for the development of an autonomous electric vehicle. In particular, it focuses on the design of the electrical architecture and the control strategy, tailored around the usage of affordable sensors and actuators. The specifications of the components are extensively discussed in relation to the performance target. The aim is to provide a comprehensive guide for the development of the remotely controlled platform, in order to lower the entry barrier for the development of autonomous electric vehicles.

This paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area.

This paper examines the closed-loop characteristics of the basic CFOA, and in particular, the dynamic response.  Additionally, it also examines the design and advantages of the CFOA regarding its ability to provide a significantly constant closed-loop bandwidth for closed-loop voltage gain. Secondly, the almost limitless slew–rate provided by the class AB input stage that makes it superior to the VOA counterpart. Additionally; this paper also concerns the definitions and measurements of the terminal parameters of the CFOA, regarded as a ‘black box’. It does not deal with the way that these parameters are related to the properties of the active passive and active components of a particular circuit configuration. Simulation is used in terminal parameter determination: this brings with it the facility of using test conditions that would not normally prevail in a laboratory test on silicon implementations of the CFOAs. Thus, we can apply 1mA and 1mV test signals from, respectively, infinite and zero source impedances that range in frequency from d.c to some tens of GHz. Also, we assume the existence of resistors with identical Ohmic value and very high value ideal capacitors. Where appropriate, practical test methods are referred to physical laboratory prototypes.

This paper describes the design and operation of a high output impedance tissue current driver circuit, for use in medical electronics, such as Electrical Impedance Tomography (EIT).  This novel architecture was designed for implementation in bipolar technology, to meet the specifications for EIT, namely operating frequency range 10 kHz–1 MHz with a target output resistance of 16 MW.  Simulation results are presented, showing that the current source more than met the minimum specification for EIT.

Excess phase in oscillators or phase locked loops is a very important design specification typically modelled as a continuous time signal. In this paper we explain why, when the quantity of interest is jitter, excess phase should be treated as a discrete quantity.  This treatment helps explaining noise folding in frequency dividers and analyse its consequences in Phase Locked Loops. 

An exemplary design demonstrates how to extend the common-mode rejection ratio (CMRR) bandwidth of a CMOS differential amplifier. The design presented uses MOSFETs with a channel length of 180nm. A novel circuit technique is employed that partially compensates for the output capacitance of the tail current sink, thereby more than quadrupling the CMRR bandwidth in the example considered.

A new start-up circuit configuration, with minimal standby power dissipation, is proposed for CMOS self-biased current generators. Using standard 0.13µm CMOS technology, simulation results show that for a supply voltage range 1.8V to 2.5V, and a temperature range −40ºC to +85ºC, the circuit standby power dissipation is less than 20nW.

Our goal is development of an algorithm capable of predicting the directional trend of the Standard and Poor’s 500 index (S&P 500).  Extensive research has been published attempting to predict different financial markets using historical data testing on an in-sample and trend basis, with many authors employing excessively complex mathematical techniques.  In reviewing and evaluating these in-sample methodologies, it became evident that this approach was unable to achieve sufficiently reliable prediction performance for commercial exploitation. For these reasons, we moved to an out-of-sample strategy based on linear regression analysis of an extensive set of financial data correlated with historical closing prices of the S&P 500. We are pleased to report a directional trend accuracy of greater than 55% for tomorrow (t+1) in predicting the S&P 500.

The cascode amplifier has the potential of providing high gain and high bandwidth simultaneously. However, the design is not as intuitive as one might at first think. In this paper, we present a detailed analysis of the single cascode amplifiers. The relationship between gain and bandwidth is important. When used to achieve maximum bandwidth the voltage gain of the common-source stage is close to unity. However, when the cascode is designed to obtain a high voltage gain, then the gain-bandwidth trade-off, typical in the common source amplifier, reappears. This analysis is used to provide the basis for practical cascode amplifier design.

The challenge facing SerDes (Serialiser De-Serialiser) designers is common with all current communications technologies. Industry advances show a trend to increase speed, reduce power and improve efficiency. In this article a novel line driver that can operate at speeds of up to 40 Gbps with a power supply of 1-‰V and a power consumption of 4.54-‰mW/Gb/s is presented. Pre-distortion on the front-end is used to maintain signal integrity.

This paper presents a novel method of non-contact infrared thermometry optimized for remote monitoring in cold climates. The method consists of selectively heating the optics of the instrument in order to prevent ice forming on the lens and blocking infrared energy. A self-calibration method is used to remove the errors caused by thermal shock when the heaters are cycled. Applications for this instrument include the monitoring of roads and railways to detect ice as well as long-term environmental studies. The self-calibration technique is shown to maintain an accuracy of ±1 °C in ambient temperatures as low as −20 °C. This compares with errors of over 20 °C in a conventional infrared thermometer.

The ISFET chemical current conveyor (CCCII+) was first reported by the authors at ISCAS 2008. In this paper a new application of the CCCII+ is presented, namely to provide a direct means of measuring cell and bacterial activity. The measurement system is based on an array of unmodified ISFET CCCII+ sensors each of which when operated in weak inversion gives an output corresponding to the time derivative of hydrogen ions. Combining each of the CCCII+ time derivative outputs in the array using the analog computational versatility of the CCCII+ current output stage provides a signal corresponding to cell and bacterial activity. The design has been fully simulated using Triple-well 0.18-μm CMOS technology and the results presented in this paper show that a viable system for direct measurement of cell and bacterial activity can be obtain, further confirming the utility of the CCCII+ for another biochemical sensing application.

The theoretical background and a selection of simulated results are presented for a 10-‰µA PTAT current generator that is a modified CMOS version of an existing bipolar configuration. Using standard 0.35-‰µm CMOS technology, the circuit exhibits a current variation of less than 0.01% when the supply rail voltage is changed from 0.5 to 10-‰V.

Operating from a 1 V rail supply, a proposed CMOS current-controlled DC current generator can function as a repeater, attenuator or amplifier over the input current range, 1 µA to 1 mA, with a current-transfer ratio accuracy better than 1% using IBM technology, characterised by a process with a 0.13 µm minimum feature size. In repeater mode, the incremental output resistance exceeds 30 MΩ for an output current of 500 µA at an output voltage of 0.20 V, and exceeds 1 MΩ for an output current of 1 mA at an output voltage of 0.22 V. For zero input current, the circuit dissipation is 117 µW

A system potentially capable of providing continuous analogue computation of (i) urea concentration, (ii) creatinine concentration and (iii) urea-to-creatinine ratio, important markers for the prediction of renal failure is described. The system utilises two enzyme modified chemical current-conveyors, CCCII+, to obtain the outputs directly related to the urea and creatinine concentrations. The devices have been separately prepared by immobilising urease and creatinine deiminase (CD) enzymes onto the input ISFET surfaces. The primary experimental results of the system demonstrate a linear response covering a normal physiological range of urea between 2.5 and 8.3 mM and creatinine between 44 and 106 μM. We propose that this system has the potential for real-time monitoring and suitable for medical determination for renal dysfunctionality.

This paper presents a self-calibration technique for the removal of measurement errors caused by thermal gradients in thermopile-based infrared thermometry, particularly when measuring low temperatures. Applications for this self-calibration method include low-temperature measurement in the food industry and infrared thermometers for remote temperature monitoring in cold climates. The self-calibration technique reported in this paper is shown to reduce the measurement error to within $pm 1 ^{circ}hbox{C}$ within 5 s of an extreme thermal shock, compared with an uncompensated thermometer that does not recover until the thermal gradient is removed. The root-mean-square temperature noise for the duration of the thermal shock test is less than 0.2 $^{circ}hbox{C}$. This technique is the subject of a patent application and can be applied to any infrared thermometer utilizing a thermopile, regardless of the thermopile size and geometry.

The ion sensitive field effect transistor (ISFET) is a popular sensor in biomedical electronics and has been used to date mainly for relatively low speed applications, such as measurement of pH of common biomedical fluids. However, there is a growing interest in sensing rapidly changing ion activity for applications including chemical synapse and rapid DNA sequencing. In this reported work, it is demonstrated that the response time of the ISFET is sufficient for these applications. The results obtained are used to determine the factors that affect high speed chemical sensing with the ISFET.

The input stage design in current-feedback operational amplifiers (CFOAs) is primarily responsible for determining the performance of the amplifier, including input voltage range, input referred offset voltage and DC input current. This paper focuses on analysis of the input stage of the conventional CFOA. The outcome of the work gives clear insight into the operation of the CFOA and establishes the mechanisms responsible for determining these parameters.

The pH and buffer index/capacity of a biomedical fluid, such as blood, provide useful clinical data for decisions on diagnosis and appropriate treatment. In this paper a novel system that has the capability of producing a useful miniaturised biosensor based, clinical instrument system providing simultaneous outputs of both pH and buffer index/capacity (β) is described. The system uses an ISFET as the primary sensing element and is based on the author's chemical current conveyor (CCCII+). A prototype has been constructed, and the results verify both the concept and viability of practical measuring system for pH and β.

A novel circuit design technique is presented which improves gain-accuracy and linearity in differential amplifiers. The technique employs negative impedance compensation and results demonstrate a significant performance improvement in precision, lowering sensitivity, and wide dynamic range. A theoretical underpinning is given together with the results of a demonstrator differential input/output amplifier with gain of 12 dB. The simulation results show that, with the novel method, both the gain-accuracy and linearity can be improved greatly. Especially, the linearity improvement in IMD can get to more than 23 dB with a required gain.