Dr Abusaleh Jabir

Dr Abusaleh Jabir, with Dr Balwinder Raj, Prof Ahmed Hemani (KTH Sweden), and Dr Saurabh Khandelwal, edited and authored a book "Nanoscale Memristor Device and Circuits Design" which is now published with the Elsevier Publishers (Nanotechnology Series). This book addresses some of the cutting edge research carried out and the key challenges in this emerging technology with applications in memory and logic design, neuromorphic and in-memory computing, chemical sensing, and cybersecurity. Four of the twelve chapters in this book are co-authored by Dr Jabir's former and current doctoral students with him.

Integrated Circuit (IC) verification, i.e. the process of ensuring that it performs according to the design specifications, is highly resource intensive. This often depends on an IC’s complexity, e.g. the number of gates/transistors which translates into expressions, branches, blocks, etc in its high level descriptions. To reduce overall verification and hence design time, industries resort to “Regression Testing” where a very small test suite, with very high test coverage, is selected to verify any modified design block and its dependencies. One of the key steps in regression test-based verification is distributing the tests to the various interconnected blocks under tests based on their functionality and accessibility, which translates into a block’s “connection strengths” among other parameters. The existing approaches currently define the connection strengths manually by the design experts which often lead to inconsistency in the test results. In this paper, we propose a Graph Neural Network (GNN) based approach to estimate the connection strengths of different interconnected blocks and evaluate its effectiveness with industrial designs in conjunction with a technique called “SMART Regression” compared to random and full regression
testing.

Memristors, typically considered for their non-volatile resistive memory for high-density memory designs, have shown very good sensitivity to various chemicals. As such, these devices can also be fabricated as chemical sensors with intrinsic memory. When fabricated for sensing chemicals, the switching state of the devices, depending on the amount of the applied bias voltage/current, also changes in the presence of the
chemicals, compared to when the chemicals are not present. We have observed that this property can be combined with the device’s intrinsic memory to directly digitise sensed information. To this end, in this paper, we propose an innovative technique to directly digitise the sensor readings, e.g. gas concentrations,
simply by pulsing the devices to exploit the memory behaviour in the presence of a chemical to change the state of the device. Essentially, we are relying on the sensors to tell us when a certain property of a chemical is sensed by switching its state while this information is digitised. This method obviates the need
to use separate Analogue-to-Digital converters (ADC), thereby significantly simplifying the sensor architecture in terms of power consumption and circuit complexity. Additionally, owing to the observed high non-linearity of the fabricated devices, this digitisation method is also highly nonlinear, which can provide
an added layer of security in the sensed information.

Memristors are finding applications in memory, logic, neuromorphic systems, and data security. To this end, we leverage the non-linear behaviour of memristors to devise a low overhead physical unclonable function using a memristive chaos circuit in conjunction with a non-linear memristive encoder. We demonstrate the effectiveness of this architecture in Challenge-Response-Pair based authentication, and for its physical uncloneability. This architecture is highly versatile and can be implemented with a single encoder or a number of encoders running in parallel, each one with its own merit, for extending the sizes of CRPs. To demonstrate its effectiveness, we subject the architecture to machine learning based modelling attacks e.g. Logistic Regression, Support Vector
Machines, Random Forest, as well as Artificial Neural Network classifiers. We found out that the proposed PUF architecture provides better resistance to such attacks, even for smaller bit sizes and at reduced overheads.

Sensors give factual and process information about the environment or other physical phenomena. Sensing using memristors has been recently introduced for its potential for high density integration and miniaturization. Complementary Resistive Switch (CRS) based sensor provides an extremely efficient crossbar array that reduces the sneak current. The objective of this paper is to introduce and evaluate a circuit model for sensing using memristive complementary resistive switch. We introduce a reliable SPICE implementation of memristor model that captures the sensing behaviour of memristor. Our simulation results also validate the SPICE model for CRS sensing architecture, whose parameters could be easily adapted to match experimental data. The results also investigate the sensitivity and device behaviour of memristor and CRS sensor device in the presence of oxidizing and reducing gases of different concentration.

This paper proposes a method to calculate the yield of a memristor based sensor array considered as the
probability that the chip provides acceptable sensing results when the array is affected by manufacturing defects. The modeling is based on a Markov Chain approach, in which each state represents an operating chip configuration and the state transitions take into account manufacturing defects. The proposed method is applicable to evaluate the yield with different fault models to achieve the comparative yield obtained
by several redundancy allocations.

Memristors are an attractive option for use in future architectures due to their non-volatility, high density and low power operation. Gas sensing is one of the proposed application of memristive devices. In spite of these advantages, memristors are susceptible to defect densities due to the nondeterministic nature of nano-scale fabrication. In this paper, a novel spice memristor model incorporating fault models that emulates the gas sensing behaviour with/without faults is developed for simulation and integration with design automation tools. Our simulation results show that the proposed non-linear model detects the presence of the oxidising/reducing gas and analyses the defects/faults affecting the functionality of the sensor.

Memristor is being considered as a game changer for the realization of neuromorphic hardware systems due to its similarity with biological synapse. Recent studies show that memristor crossbar can provide high density and high performance neural network hardware implementation at low power due to its physical layout, nano scale size and low power consumption feature. This paper describes the training method that can be used for the implementation of memristive multi-layer neural network with ex-situ method. We mimic the behavior of memristor crossbar in software training process to achieve more accurate and close computations to hardware. Voltage divider has been used to calculate the dot product in this method. To demonstrate the accuracy and effectiveness of this method, different patterns and non-separable functions using memristor crossbar structures are simulated. The results demonstrate that more accurate computations can be produced using this learning method for ex-situ. It also reduces the learning time of functions.

Among these emerging technologies is the memristor-based resistive random access memory (ReRAM) with simpler structures and capability of producing highly dense memory through the

sneak-path prone crossbar architecture. In this paper, a multiplecells read solution to reduce the overall energy consumption when reading from a memory array is considered. A closed form

expression for the noise margin effect is derived and analysis shows that there is zero sneak-path when sensing certain patterns of stored data. The multiple-cells readout method was thus used to analyse an energy efficient Inverted-Hamming (I-H) architecture capable of detecting and correcting single-bit write error in memristor-based memory array.

Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and reliable implementation of cryptographic algorithms in hardware must be able to detect or correct such malicious attacks. Error detection/correction (EDC), through fault tolerance, could be an effective way to mitigate such fault attacks in cryptographic hardware. To this end, we analyze the area, delay, and power overhead for designing the S-Box, which is one of the main complex blocks in the Advanced Encryption Standard (AES), with error detection and correction capability. We use multiple Parity Predictions (PPs), based on various error correcting codes, to detect and correct errors. Various coding techniques are presented, which include simple parity prediction, split parity codes, Hamming, Hsiao, and LDPC codes. The S-Box, GF(p), and PP circuits are synthesized from the specifications, while the decoding and correction circuits are combined to form the complete designs. The analysis shows a comparison of the different approaches characterized by their error detection capability.